DECIDER: A Decision Diagram Based Hierarchical Test Generation System
نویسندگان
چکیده
Current paper presents a hierarchical test pattern generation system that uses register-transfer level VHDL and gate-level EDIF netlist descriptions as inputs. The system includes appropriate interfaces to synthesize Decision Diagram (DD) models, a DD based test pattern generator and a fault simulator to evaluate the quality of the generated tests. In the paper, the structure of the system is presented. Additionally, representation of different design abstraction levels using decision diagrams is explained. The performance of the system is compared to other state-of-the-art tools for sequential circuit test generation.
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